Information

DMA_HRS field descriptions (continued)
Field Description
4
HRS4
Hardware Request Status Channel 4
0 A hardware service request for the corresponding channel is not present
1 A hardware service request for the corresponding channel is present
3
HRS3
Hardware Request Status Channel 3
0 A hardware service request for the corresponding channel is not present
1 A hardware service request for the corresponding channel is present
2
HRS2
Hardware Request Status Channel 2
0 A hardware service request for the corresponding channel is not present
1 A hardware service request for the corresponding channel is present
1
HRS1
Hardware Request Status Channel 1
0 A hardware service request for the corresponding channel is not present
1 A hardware service request for the corresponding channel is present
0
HRS0
Hardware Request Status Channel 0
0 A hardware service request for the corresponding channel is not present
1 A hardware service request for the corresponding channel is present
21.3.16 Channel n Priority Register (DMA_DCHPRIn)
When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the contents of these
registers define the unique priorities associated with each channel. The channel priorities
are evaluated by numeric value; for example, 0 is the lowest priority, 1 is the next
priority, then 2, 3, etc. Software must program the channel priorities with unique values.
Otherwise, a configuration error is reported. The range of the priority value is limited to
the values of 0 through 15.
Addresses: 4000_8000h base + 100h offset + (1d × n), where n = 0d to 15d
Bit 7 6 5 4 3 2 1 0
Read
ECP DPA
0
CHPRI
Write
Reset
x* x* x* x* x* x* x* x*
* Notes:
x = Undefined at reset.•
DMA_DCHPRIn field descriptions
Field Description
7
ECP
Enable Channel Preemption
Table continues on the next page...
Memory map/register definition
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
454 Freescale Semiconductor, Inc.