Information

DMA_DCHPRIn field descriptions (continued)
Field Description
0 Channel n cannot be suspended by a higher priority channel’s service request
1 Channel n can be temporarily suspended by the service request of a higher priority channel
6
DPA
Disable Preempt Ability
0 Channel n can suspend a lower priority channel
1 Channel n cannot suspend any channel, regardless of channel priority
5–4
Reserved
This read-only field is reserved and always has the value zero.
3–0
CHPRI
Channel n Arbitration Priority
Channel priority when fixed-priority arbitration is enabled
NOTE: Reset value for the channel priority fields, CHPRI, is equal to the corresponding channel number
for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
21.3.17 TCD Source Address (DMA_TCD_SADDR)
Addresses: 4000_8000h base + 1000h offset + (32d × n), where n = 0d to 15d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
SADDR
W
Reset
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
x = Undefined at reset.•
DMA_TCDn_SADDR field descriptions
Field Description
31–0
SADDR
Source Address
Memory address pointing to the source data.
Chapter 21 Direct Memory Access Controller (eDMA)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 455