Information

Section Number Title Page
Chapter 47
Integrated interchip sound (I2S)
47.1 Introduction...................................................................................................................................................................1449
47.1.1 Block diagram..............................................................................................................................................1449
47.1.2 Features........................................................................................................................................................1450
47.1.3 Modes of operation......................................................................................................................................1451
47.2 I2S signal descriptions..................................................................................................................................................1453
47.3 Memory map/register definition...................................................................................................................................1457
47.3.1 I
2
S Transmit Data Registers 0 (I2Sx_TX0).................................................................................................1459
47.3.2 I
2
S Transmit Data Registers 1 (I2Sx_TX1).................................................................................................1459
47.3.3 I
2
S Receive Data Registers 0 (I2Sx_RX0)...................................................................................................1460
47.3.4 I
2
S Receive Data Registers 1 (I2Sx_RX1)...................................................................................................1460
47.3.5 I
2
S Control Register (I2Sx_CR)...................................................................................................................1461
47.3.6 I
2
S Interrupt Status Register (I2Sx_ISR).....................................................................................................1464
47.3.7 I
2
S Interrupt Enable Register (I2Sx_IER)....................................................................................................1469
47.3.8 I
2
S Transmit Configuration Register (I2Sx_TCR).......................................................................................1473
47.3.9 I
2
S Receive Configuration Register (I2Sx_RCR)........................................................................................1475
47.3.10 I
2
S Transmit Clock Control Registers (I2Sx_TCCR)..................................................................................1477
47.3.11 I
2
S Receive Clock Control Registers (I2Sx_RCCR)...................................................................................1479
47.3.12 I
2
S FIFO Control/Status Register (I2Sx_FCSR)..........................................................................................1480
47.3.13 I
2
S AC97 Control Register (I2Sx_ACNT)...................................................................................................1486
47.3.14 I
2
S AC97 Command Address Register (I2Sx_ACADD).............................................................................1487
47.3.15 I
2
S AC97 Command Data Register (I2Sx_ACDAT)...................................................................................1488
47.3.16 I
2
S AC97 Tag Register (I2Sx_ATAG)........................................................................................................1488
47.3.17 I
2
S Transmit Time Slot Mask Register (I2Sx_TMSK)................................................................................1489
47.3.18 I
2
S Receive Time Slot Mask Register (I2Sx_RMSK).................................................................................1489
47.3.19 I
2
S AC97 Channel Status Register (I2Sx_ACCST).....................................................................................1490
47.3.20 I
2
S AC97 Channel Enable Register (I2Sx_ACCEN)...................................................................................1490
47.3.21 I
2
S AC97 Channel Disable Register (I2Sx_ACCDIS).................................................................................1491
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
46 Freescale Semiconductor, Inc.