Information

DMA_TCDn_DLASTSGA field descriptions (continued)
Field Description
else
• This address points to the beginning of a 0-modulo-32-byte region containing the next transfer
control descriptor to be loaded into this channel. This channel reload is performed as the major
iteration count completes. The scatter/gather address must be 0-modulo-32-byte, else a
configuration error is reported.
21.3.29 TCD Control and Status (DMA_TCD_CSR)
Addresses: 4000_8000h base + 101Ch offset + (32d × n), where n = 0d to 15d
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
BWC
0
MAJORLINKCH
DONE
ACTIVE
MAJORELINK
ESG
DREQ
INTHALF
INTMAJOR
START
Write
Reset
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
x = Undefined at reset.•
DMA_TCDn_CSR field descriptions
Field Description
15–14
BWC
Bandwidth Control
Throttles the amount of bus bandwidth consumed by the eDMA. In general, as the eDMA processes the
minor loop, it continuously generates read/write sequences until the minor count is exhausted. This field
forces the eDMA to stall after the completion of each read/write access to control the bus request
bandwidth seen by the crossbar switch.
NOTE: If the source and destination sizes are equal, this field is ignored between the first and second
transfers and after the last write of each minor loop. This behavior is a side effect of reducing
start-up latency.
00 No eDMA engine stalls
01 Reserved
10 eDMA engine stalls for 4 cycles after each r/w
11 eDMA engine stalls for 8 cycles after each r/w
13–12
Reserved
This read-only field is reserved and always has the value zero.
11–8
MAJORLINKCH
Link Channel Number
If (MAJORELINK = 0) then
• No channel-to-channel linking (or chaining) is performed after the major loop counter is exhausted.
else
Table continues on the next page...
Memory map/register definition
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
464 Freescale Semiconductor, Inc.