Information

1
eDMA Engine
Data Path
eDMA
0
Program Model/
64
Control
n-1
To/From Crossbar Switch
2
Channel Arbitration
Address Path
Read Data
Write Data
Address
Read Data
Write Data
Write Address
eDMA Peripheral
Request
eDMA Done
Transfer
Control
Descriptor (TCD)
Internal Peripheral Bus
Figure 21-291. eDMA operation, part 3
21.4.2 Error reporting and handling
Channel errors are reported in the ES register and can be caused by:
• A configuration error, which is an illegal setting in the transfer-control descriptor or
an illegal priority register setting in Fixed-Arbitration mode, or
• An error termination to a bus master read or write cycle
A configuration error is reported when the starting source or destination address, source
or destination offsets, minor loop byte count, or the transfer size represent an inconsistent
state. Each of these possible causes are detailed below:
• The addresses and offsets must be aligned on 0-modulo-transfer-size boundaries.
• The minor loop byte count must be a multiple of the source and destination transfer
sizes.
Chapter 21 Direct Memory Access Controller (eDMA)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 471