Information

Section Number Title Page
50.1.2 Features........................................................................................................................................................1562
50.1.3 Modes of operation......................................................................................................................................1562
50.2 External signal description............................................................................................................................................1564
50.2.1 TCK—Test clock input................................................................................................................................1564
50.2.2 TDI—Test data input...................................................................................................................................1564
50.2.3 TDO—Test data output................................................................................................................................1564
50.2.4 TMS—Test mode select...............................................................................................................................1564
50.3 Register description......................................................................................................................................................1565
50.3.1 Instruction register.......................................................................................................................................1565
50.3.2 Bypass register.............................................................................................................................................1565
50.3.3 Device identification register.......................................................................................................................1565
50.3.4 Boundary scan register.................................................................................................................................1566
50.4 Functional description...................................................................................................................................................1567
50.4.1 JTAGC reset configuration..........................................................................................................................1567
50.4.2 IEEE 1149.1-2001 (JTAG) Test Access Port..............................................................................................1567
50.4.3 TAP controller state machine.......................................................................................................................1567
50.4.4 JTAGC block instructions............................................................................................................................1569
50.4.5 Boundary scan..............................................................................................................................................1572
50.5 Initialization/Application information..........................................................................................................................1572
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 49