Information

23.4.2 Byte Test
The byte test implements more thorough a test of the watchdog timer. In this test, the
timer is split up into its constituent byte-wide stages that are run independently and tested
for time-out against the corresponding byte of the time-out value register. The following
figure explains the splitting concept:
CLK
WDOG
en
Mod = = Timer?
Test
32-bit Timer
Modulus Register
(Time-out Value)
WDOG
Reset
Nth Stage Overflow Enables N + 1th Stage
en en
Reset Value (Hardwired)
Byte
Stage 4
Equality Comparison
Byte 4
Byte 2
Byte 1
Byte 3
Byte
Stage 3
Byte
Stage 2
Byte
Stage 1
Figure 23-2. Watchdog Timer Byte Splitting
Each stage is an 8-bit synchronous counter followed by combinational logic that
generates an overflow signal. The overflow signal acts as an enable to the N + 1th stage.
In the test mode, when an individual byte, N, is tested, byte N – 1 is loaded forcefully
with 0xFF, and both these bytes are allowed to run off the clock source. By doing so the
overflow signal from stage N – 1 is generated immediately, enabling counter stage N.
The Nth stage runs and compares with the Nth byte of the time-out value register. In this
way, the byte N is also tested along with the link between it and the preceding stage. No
other stages, N – 2, N – 3... and N + 1, N + 2... are enabled for the test on byte N. These
disabled stages (except the most significant stage of the counter) are loaded with a value
of 0xFF.
These two testing schemes achieve the overall aim of testing the counter functioning and
the compare and reset logic.
Chapter 23 Watchdog Timer (WDOG)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 507