Information

• A gap of more than 20 bus cycles exists between the writes of two values of the
unlock sequence.
• A gap of more than 20 bus cycles exists between the writes of two values of the
refresh sequence.
The watchdog can also generate an interrupt. If IRQ_RST_EN is set, then on the above
mentioned events WDOG_ST_CTRL_L[INT_FLG] is set, generating an interrupt. A
watchdog reset is also generated WCT time later to ensure the watchdog is fault tolerant.
The interrupt can be cleared by writing 1 to INT_FLG.
The gap of WCT time between interrupt and reset means that the WDOG time-out value
must be greater than WCT. Otherwise, if the interrupt was generated due to a time-out, a
second consecutive time-out will occur in that WCT gap. This will trigger the backup
reset generator to generate a reset to the system, prematurely ending the interrupt service
routine execution. Also, the jobs like counting the number of watchdog resets would not
be done.
23.7 Memory Map and Register Definition
This section consists of the memory map and register descriptions.
WDOG memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4005_2000
Watchdog Status and Control Register High
(WDOG_STCTRLH)
16 R/W 01D3h
23.7.1/
510
4005_2002
Watchdog Status and Control Register Low
(WDOG_STCTRLL)
16 R/W 0001h
23.7.2/
512
4005_2004 Watchdog Time-out Value Register High (WDOG_TOVALH) 16 R/W 004Ch
23.7.3/
512
4005_2006 Watchdog Time-out Value Register Low (WDOG_TOVALL) 16 R/W 4B4Ch
23.7.4/
513
4005_2008 Watchdog Window Register High (WDOG_WINH) 16 R/W 0000h
23.7.5/
513
4005_200A Watchdog Window Register Low (WDOG_WINL) 16 R/W 0010h
23.7.6/
514
4005_200C Watchdog Refresh Register (WDOG_REFRESH) 16 R/W B480h
23.7.7/
514
Table continues on the next page...
Chapter 23 Watchdog Timer (WDOG)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 509