Information

takes place only when the complete 16-bit value is correctly written, write4. Hence, the
requirement of writing value2 of the sequence within 20 bus clock cycles of value1 is
checked by measuring the gap between write2 and write4.
It is reiterated that the condition for matching values 1 and 2 of the refresh or unlock
sequence remains unchanged. It is just the criterion for detecting a wrong value in these
registers which has been relaxed, as explained, for 8-bit accesses. Any 16-bit access still
needs to adhere to the original guidelines, mentioned in the sections Refreshing the
Watchdog.
23.9 Restrictions on Watchdog Operation
This section mentions some exceptions to the watchdog operation that may not be
apparent to you.
• Restriction on unlock / refresh operations—In the period between the closure of the
WCT window (after unlock) and the actual reload of the watchdog timer, unlock and
refresh operations need not be attempted.
• The update and reload of the watchdog timer happens two to three watchdog clocks
after WCT window closes, following a successful configuration on unlock.
• Clock Switching Delay—The watchdog uses glitch free multiplexers at two places –
one to choose between the LPO oscillator input and alternate clock input and the
other to choose between the watchdog functional clock and fast clock input for
watchdog functional test. A maximum time period of ~ 2 clock A cycles plus ~2
clock B cycles elapses from the time a switch is requested to the occurrence of the
actual clock switch (clock A and B are the two input clocks to the clock mux).
• For the windowed mode, there is a two to three bus clock latency between the
watchdog counter going past the window value and the same registering in the bus
clock domain.
• For proper operation of the watchdog, the watchdog clock must be at least five times
slower than the system bus clock at all times. An exception is the case when the
watchdog clock is synchronous to the bus clock wherein the watchdog clock can be
as fast as the bus clock.
• WCT must be equivalent to at least three watchdog clock cycles. If not ensured, this
means that even after the close of the WCT window, you have to wait for the
synchronized system reset to deassert in the watchdog clock domain, before
expecting the configuration updates to take effect.
Restrictions on Watchdog Operation
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
518 Freescale Semiconductor, Inc.