Information

24.1.2 Modes of Operation
There are nine modes of operation for the MCG: FEI, FEE, FBI, FBE, PBE, PEE, BLPI,
BLPE, and Stop. For details, see MCG Modes of Operation.
24.2 External Signal Description
There are no MCG signals that connect off chip.
24.3 Memory Map/Register Definition
This section includes the memory map and register definition.
The MCG registers can only be written to when in supervisor mode. Write accesses when
in user mode will result in a bus error. Read accesses may be performed in both
supervisor and user modes.
MCG memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4006_4000 MCG Control 1 Register (MCG_C1) 8 R/W 04h
24.3.1/
526
4006_4001 MCG Control 2 Register (MCG_C2) 8 R/W See section
24.3.2/
527
4006_4002 MCG Control 3 Register (MCG_C3) 8 R/W Undefined
24.3.3/
528
4006_4003 MCG Control 4 Register (MCG_C4) 8 R/W Undefined
24.3.4/
529
4006_4004 MCG Control 5 Register (MCG_C5) 8 R/W 00h
24.3.5/
530
4006_4005 MCG Control 6 Register (MCG_C6) 8 R/W 00h
24.3.6/
532
4006_4006 MCG Status Register (MCG_S) 8 R 10h
24.3.7/
533
4006_4008 MCG Auto Trim Control Register (MCG_ATC) 8 R/W 00h
24.3.8/
535
4006_400A
MCG Auto Trim Compare Value High Register
(MCG_ATCVH)
8 R/W 00h
24.3.9/
535
4006_400B
MCG Auto Trim Compare Value Low Register
(MCG_ATCVL)
8 R/W 00h
24.3.10/
536
Chapter 24 Multipurpose Clock Generator (MCG)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 525