Information

MCG_C5 field descriptions (continued)
Field Description
0 MCGPLLCLK is inactive.
1
MCGPLLCLK is active.
5
PLLSTEN
PLL Stop Enable
Enables the PLL Clock during Normal Stop (In Low Power Stop mode, the PLL clock gets disabled
even if PLLSTEN =1). All other power modes, PLLSTEN bit has no affect and does not enable the PLL
Clock to run if it is written to 1.
0 MCGPLLCLK is disabled in any of the Stop modes.
1
MCGPLLCLK is enabled if system is in Normal Stop mode.
4–0
PRDIV
PLL External Reference Divider
Selects the amount to divide down the external reference clock for the PLL. The resulting frequency
must be in the range of 2 MHz to 4 MHz. After the PLL is enabled (by setting either PLLCLKEN or
PLLS), the PRDIV value must not be changed when LOCK is zero.
Table 24-7. PLL External Reference Divide Factor
PRDIV Divide
Factor
PRDIV Divide
Factor
PRDIV Divide
Factor
PRDIV Divide
Factor
00000 1 01000 9 10000 17 11000 25
00001 2 01001 10 10001 18 11001 Reserv
ed
00010 3 01010 11 10010 19 11010 Reserv
ed
00011 4 01011 12 10011 20 11011 Reserv
ed
00100 5 01100 13 10100 21 11100 Reserv
ed
00101 6 01101 14 10101 22 11101 Reserv
ed
00110 7 01110 15 10110 23 11110 Reserv
ed
00111 8 01111 16 10111 24 11111 Reserv
ed
Chapter 24 Multipurpose Clock Generator (MCG)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 531