Information

Table 24-15. MCGOUTCLK Frequency Calculation Options
Clock Mode f
MCGOUTCLK
1
Note
FEI (FLL engaged internal) (f
int
* F) Typical f
MCGOUTCLK
= 20 MHz
immediately after reset.
FEE (FLL engaged external) (f
ext
/ FLL_R) *F f
ext
/ FLL_R must be in the range of
31.25 kHz to 39.0625 kHz
FBE (FLL bypassed external) f
ext
f
ext
/ FLL_R must be in the range of
31.25 kHz to 39.0625 kHz
FBI (FLL bypassed internal) f
int
Typical f
int
= 32 kHz
PEE (PLL engaged external) (f
ext
/ PLL_R) * M f
ext
/ PLL_R must be in the range of
2 – 4 MHz
PBE (PLL bypassed external) f
ext
f
ext
/ PLL_R must be in the range of
2 – 4 MHz
BLPI (Bypassed low power internal) f
int
BLPE (Bypassed low power external) f
ext
1. FLL_R is the reference divider selected by the C1[FRDIV] bits, PLL_R is the reference divider selected by C5[PRDIV] bits,
F is the FLL factor selected by C4[DRST_DRS] and C4[DMX32] bits, and M is the multiplier selected by C6[VDIV] bits.
This section will include 3 mode switching examples using an 4 MHz external crystal. If
using an external clock source less than 2 MHz, the MCG should not be configured for
any of the PLL modes (PEE and PBE).
24.5.3.1 Example 1: Moving from FEI to PEE Mode : External Crystal
= 4 MHz, MCGOUTCLK Frequency = 48 MHz
In this example, the MCG will move through the proper operational modes from FEI to
PEE to achieve 48 MHz MCGOUTCLK frequency from 4 MHz external crystal
reference. First, the code sequence will be described. Then a flowchart will be included
which illustrates the sequence.
1. First, FEI must transition to FBE mode:
a. C2 = 0x1C
• C2[RANGE] set to 2'b01 because the frequency of 4 MHz is within the high
frequency range
• C2[HGO] set to 1 to configure the crystal oscillator for high gain operation
• C2[EREFS] set to 1, because a crystal is being used
b. C1 = 0x90
Initialization / Application Information
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
548 Freescale Semiconductor, Inc.