Information

Table 2-4. Memories and memory interfaces (continued)
Module Description
System register file 32-byte register file that is accessible during all power modes and is powered by
VDD.
VBAT register file 32-byte register file that is accessible during all power modes and is powered by
VBAT.
Serial programming interface (EzPort) Same serial interface as, and subset of, the command set used by industry-
standard SPI flash memories. Provides the ability to read, erase, and program
flash memory and reset command to boot the system after flash programming.
FlexBus External bus interface with multiple independent, user-programmable chip-select
signals that can interface with external SRAM, PROM, EPROM, EEPROM, flash,
and other peripherals via 8-, 16- and 32-bit port sizes. Configurations include
multiplexed or non-multiplexed address and data buses using 8-bit, 16-bit, 32-bit,
and 16-byte line-sized transfers.
2.3.4 Clocks
The following clock modules are available on this device.
Table 2-5. Clock modules
Module Description
Multi-clock generator (MCG) The MCG provides several clock sources for the MCU that include:
• Phase-locked loop (PLL) — Voltage-controlled oscillator (VCO)
• Frequency-locked loop (FLL) — Digitally-controlled oscillator (DCO)
• Internal reference clocks — Can be used as a clock source for other on-chip
peripherals
System oscillator The system oscillator, in conjunction with an external crystal or resonator,
generates a reference clock for the MCU.
Real-time clock oscillator The RTC oscillator has an independent power supply and supports a 32 kHz
crystal oscillator to feed the RTC clock. Optionally, the RTC oscillator can replace
the system oscillator as the main oscillator source.
2.3.5 Security and Integrity modules
The following security and integrity modules are available on this device:
Table 2-6. Security and integrity modules
Module Description
Cyclic Redundancy Check (CRC) Hardware CRC generator circuit using 16/32-bit shift register. Error detection for
all single, double, odd, and most multi-bit errors, programmable initial seed value,
and optional feature to transpose input data and CRC result via transpose register.
Chapter 2 Introduction
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 57