Information

Table 27-3. Program visible cache registers
Cache
storage
Based at
offset
Contents of 32-bit read Nomenclature Nomenclature example
Tag 100h 13'h0, tag[18:6], 5'h0, valid In TAGVDWxSy, x denotes the way
and y denotes the set.
TAGVDW2S0 is the 13-bit
tag and 1-bit valid for cache
entry way 2, set 0.
Data 200h Upper or lower word of data In DATAWxSyU and DATAWxSyL,
x denotes the way, y denotes the
set, and U and L represent upper
and lower word, respectively.
DATAW1S0U represents bits
[63:32] of data entry way 1,
set 0, and DATAW1S0L
represents bits [31:0] of data
entry way 1, set 0.
FMC memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4001_F000 Flash Access Protection Register (FMC_PFAPR) 32 R/W 00F8_003Fh
27.4.1/
581
4001_F004 Flash Bank 0 Control Register (FMC_PFB0CR) 32 R/W 3002_001Fh
27.4.2/
584
4001_F008 Flash Bank 1 Control Register (FMC_PFB1CR) 32 R/W 3002_001Fh
27.4.3/
587
4001_F100 Cache Tag Storage (FMC_TAGVDW0S0) 32 R/W 0000_0000h
27.4.4/
589
4001_F104 Cache Tag Storage (FMC_TAGVDW0S1) 32 R/W 0000_0000h
27.4.4/
589
4001_F108 Cache Tag Storage (FMC_TAGVDW0S2) 32 R/W 0000_0000h
27.4.4/
589
4001_F10C Cache Tag Storage (FMC_TAGVDW0S3) 32 R/W 0000_0000h
27.4.4/
589
4001_F110 Cache Tag Storage (FMC_TAGVDW0S4) 32 R/W 0000_0000h
27.4.4/
589
4001_F114 Cache Tag Storage (FMC_TAGVDW0S5) 32 R/W 0000_0000h
27.4.4/
589
4001_F118 Cache Tag Storage (FMC_TAGVDW0S6) 32 R/W 0000_0000h
27.4.4/
589
4001_F11C Cache Tag Storage (FMC_TAGVDW0S7) 32 R/W 0000_0000h
27.4.4/
589
4001_F120 Cache Tag Storage (FMC_TAGVDW1S0) 32 R/W 0000_0000h
27.4.5/
590
4001_F124 Cache Tag Storage (FMC_TAGVDW1S1) 32 R/W 0000_0000h
27.4.5/
590
4001_F128 Cache Tag Storage (FMC_TAGVDW1S2) 32 R/W 0000_0000h
27.4.5/
590
4001_F12C Cache Tag Storage (FMC_TAGVDW1S3) 32 R/W 0000_0000h
27.4.5/
590
Table continues on the next page...
Memory map and register descriptions
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
576 Freescale Semiconductor, Inc.