Information

FMC memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4001_F2F0 Cache Data Storage (upper word) (FMC_DATAW3S6U) 32 R/W 0000_0000h
27.4.14/
599
4001_F2F4 Cache Data Storage (lower word) (FMC_DATAW3S6L) 32 R/W 0000_0000h
27.4.15/
600
4001_F2F8 Cache Data Storage (upper word) (FMC_DATAW3S7U) 32 R/W 0000_0000h
27.4.14/
599
4001_F2FC Cache Data Storage (lower word) (FMC_DATAW3S7L) 32 R/W 0000_0000h
27.4.15/
600
27.4.1 Flash Access Protection Register (FMC_PFAPR)
Address: FMC_PFAPR is 4001_F000h base + 0h offset = 4001_F000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
M7PFD M6PFD M5PFD M4PFD M3PFD M2PFD M1PFD M0PFD
W
Reset
0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
M7AP[1:0] M6AP[1:0] M5AP[1:0] M4AP[1:0] M3AP[1:0] M2AP[1:0] M1AP[1:0] M0AP[1:0]
W
Reset
0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
FMC_PFAPR field descriptions
Field Description
31–24
Reserved
This read-only field is reserved and always has the value zero.
23
M7PFD
Master 7 Prefetch Disable
These bits control whether prefetching is enabled based on the logical number of the requesting crossbar
switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits.
0 Prefetching for this master is enabled.
1 Prefetching for this master is disabled.
22
M6PFD
Master 6 Prefetch Disable
These bits control whether prefetching is enabled based on the logical number of the requesting crossbar
switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits.
Table continues on the next page...
Chapter 27 Flash Memory Controller (FMC)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 581