Information

FMC_PFAPR field descriptions (continued)
Field Description
This field controls whether read and write access to the flash are allowed based on the logical master
number of the requesting crossbar switch master.
00 No access may be performed by this master
01 Only read accesses may be performed by this master
10 Only write accesses may be performed by this master
11 Both read and write accesses may be performed by this master
1–0
M0AP[1:0]
Master 0 Access Protection
This field controls whether read and write access to the flash are allowed based on the logical master
number of the requesting crossbar switch master.
00 No access may be performed by this master
01 Only read accesses may be performed by this master
10 Only write accesses may be performed by this master
11 Both read and write accesses may be performed by this master
27.4.2 Flash Bank 0 Control Register (FMC_PFB0CR)
Address: FMC_PFB0CR is 4001_F000h base + 4h offset = 4001_F004h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
B0RWSC[3:0]
CLCK_WAY[3:0]
0
0 B0MW[1:0]
0
W
CINV_WAY[3:0]
S_B_
INV
Reset
0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
CRC[2:0]
B0DCE
B0ICE
B0DPE
B0IPE
B0SEBE
W
Reset
0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1
FMC_PFB0CR field descriptions
Field Description
31–28
B0RWSC[3:0]
Bank 0 Read Wait State Control
This read-only field defines the number of wait states required to access the bank 0 flash memory.
The relationship between the read access time of the flash array (expressed in system clock cycles) and
RWSC is defined as:
Access time of flash array [system clocks] = RWSC + 1
The FMC automatically calculates this value based on the ratio of the system clock speed to the flash
clock speed. For example, when this ratio is 4:1, the field's value is 3h.
Table continues on the next page...
Memory map and register descriptions
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
584 Freescale Semiconductor, Inc.