Information

FMC_PFB0CR field descriptions (continued)
Field Description
4
B0DCE
Bank 0 Data Cache Enable
This bit controls whether data references are loaded into the cache.
0 Do not cache data references.
1 Cache data references.
3
B0ICE
Bank 0 Instruction Cache Enable
This bit controls whether instruction fetches are loaded into the cache.
0 Do not cache instruction fetches.
1 Cache instruction fetches.
2
B0DPE
Bank 0 Data Prefetch Enable
This bit controls whether prefetches (or speculative accesses) are initiated in response to data references.
0 Do not prefetch in response to data references.
1 Enable prefetches in response to data references.
1
B0IPE
Bank 0 Instruction Prefetch Enable
This bit controls whether prefetches (or speculative accesses) are initiated in response to instruction
fetches.
0 Do not prefetch in response to instruction fetches.
1 Enable prefetches in response to instruction fetches.
0
B0SEBE
Bank 0 Single Entry Buffer Enable
This bit controls whether the single entry page buffer is enabled in response to flash read accesses. Its
operation is independent from bank 1's cache.
A high-to-low transition of this enable forces the page buffer to be invalidated.
0 Single entry buffer is disabled.
1 Single entry buffer is enabled.
Memory map and register descriptions
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
586 Freescale Semiconductor, Inc.