Information

PPB Modules
PPB
ARM Cortex-M4
Core
Debug Interrupts
Crossbar
switch
SRAM
Upper
SRAM
Lower
Figure 3-1. Core configuration
Table 3-1. Reference links to related information
Topic Related module Reference
Full description ARM Cortex-M4 core,
r0p0
http://www.arm.com
System memory map System memory map
Clocking Clock distribution
Power management Power management
System/instruction/data
bus module
Crossbar switch Crossbar switch
System/instruction/data
bus module
SRAM SRAM
Debug IEEE 1149.1 JTAG
IEEE 1149.7 JTAG
(cJTAG)
Serial Wire Debug
(SWD)
ARM Real-Time Trace
Interface
Debug
Interrupts Nested Vectored
Interrupt Controller
(NVIC)
NVIC
Private Peripheral Bus
(PPB) module
Miscellaneous Control
Module (MCM)
MCM
3.2.1.1 Buses, interconnects, and interfaces
The ARM Cortex-M4 core has four buses as described in the following table.
Core modules
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
64 Freescale Semiconductor, Inc.