Information

Table 29-27. FlexBus Multiplexed Operating Modes for CSCRn[BLS]=0
Port Size and Phase
FB_AD
[31:24] [23:16] [15:8] [7:0]
32-bit
Address phase Address
Data phase Data
16-bit
Address phase Address
Data phase Data Address
8-bit
Address phase Address
Data phase Data Address
Table 29-28. FlexBus Multiplexed Operating Modes for CSCRn[BLS]=1
Port Size and Phase
FB_AD
[31:24] [23:16] [15:8] [7:0]
32-bit
Address phase Address
Data phase Data
16-bit
Address phase Address
Data phase Address Data
8-bit
Address phase Address
Data phase Address Data
29.4.5 Bus Cycle Execution
As shown in Figure 29-27 and Figure 29-29, basic bus operations occur in four clocks:
1. S0: At the first clock edge, the address, attributes, and FB_TS/FB_ALE are driven.
2. S1: FB_CSn is asserted at the second rising clock edge to indicate the device
selected; by that time, the address and attributes are valid and stable. FB_TS/
FB_ALE is negated at this edge.
For a write transfer, data is driven on the bus at this clock edge and continues to be
driven until one clock cycle after
FB_CSn negates. For a read transfer, data is also
driven into the device during this cycle.
External slave asserts FB_TA at this clock edge.
3. S2: Read data and
FB_TA are sampled on the third clock edge. FB_TA can be
negated after this edge and read data can then be tri-stated.
Functional Description
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
694 Freescale Semiconductor, Inc.