Information

1. Set FB_R/W to write.
2. Place address on the external address signals.
3. Assert transfer start.
1. Decode address.
1. Start next cycle.
2. Sample FB_TA low.
External Memory/Peripheral
2. Latch data on the external address signals.
3. Assert FB_TA (external termination).
1. Negate FB_TA (external termination).
1. Select the appropriate slave device.
1. Negate transfer start.
2. Assert FB_CSn.
3. Drive data.
1. FlexBus asserts internal FB_TA
(auto acknowledge/internal termination).
FlexBus
Figure 29-28. Write-Cycle Flowchart
The following figure shows the write cycle timing diagram.
Note
The address and data busses are muxed between the FlexBus
and another module. At the end of the write bus cycles, the
address signals are indeterminate.
Functional Description
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
698 Freescale Semiconductor, Inc.