Information

Section Number Title Page
4.4 SRAM memory map.....................................................................................................................................................153
4.5 Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps...................................................................................153
4.5.1 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map........................................................................................153
4.5.2 Peripheral Bridge 1 (AIPS-Lite 1) Memory Map........................................................................................157
4.6 Private Peripheral Bus (PPB) memory map..................................................................................................................162
Chapter 5
Clock Distribution
5.1 Introduction...................................................................................................................................................................163
5.2 Programming model......................................................................................................................................................163
5.3 High-Level device clocking diagram............................................................................................................................163
5.4 Clock definitions...........................................................................................................................................................164
5.4.1 Device clock summary.................................................................................................................................165
5.5 Internal clocking requirements.....................................................................................................................................167
5.5.1 Clock divider values after reset....................................................................................................................168
5.5.2 VLPR mode clocking...................................................................................................................................168
5.6 Clock Gating.................................................................................................................................................................168
5.7 Module clocks...............................................................................................................................................................169
5.7.1 PMC 1-kHz LPO clock................................................................................................................................170
5.7.2 WDOG clocking..........................................................................................................................................170
5.7.3 Debug trace clock.........................................................................................................................................171
5.7.4 PORT digital filter clocking.........................................................................................................................171
5.7.5 LPTMR clocking..........................................................................................................................................172
5.7.6 FlexCAN clocking.......................................................................................................................................172
5.7.7 UART clocking............................................................................................................................................173
5.7.8 SDHC clocking............................................................................................................................................173
5.7.9 I2S clocking.................................................................................................................................................173
5.7.10 TSI clocking.................................................................................................................................................174
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 7