Information

Address
Address Data
TSIZ=01
AA=1
AA=0
AA=1
AA=0
FB_CLK
FB_A[Y]
FB_D[X]
FB_RW
FB_TS
FB_ALE
FB_CSn
FB_OEn
FB_BE/BWEn
FB_TA
FB_TSIZ[1:0]
Figure 29-31. Single Byte-Write Transfer
29.4.6.3.2 Bus Cycle Sizing—Word Transfer, 16-bit Device, No Wait States
The following figure illustrates the basic word read transfer to a 16-bit device with no
wait states.
• The address is driven on the full FB_AD[31:8] bus in the first clock.
• The device tristates FB_AD[31:16] on the second clock and continues to drive
address on FB_AD[15:0] throughout the bus cycle.
• The external device returns the read data on FB_AD[31:16] and may tristate the data
line or continue driving the data one clock after
FB_TA is sampled asserted.
Chapter 29 External Bus Interface (FlexBus)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 701