Information

Address
Address Data
TSIZ
AA=1
AA=0
AA=1
AA=0
FB_CLK
FB_A[Y]
FB_D[X]
FB_RW
FB_TS
FB_ALE
FB_CSn
FB_OEn
FB_BE/BWEn
FB_TA
FB_TSIZ[1:0]
Figure 29-44. Write Cycle with Two-Clock Address Setup and Two-Clock Hold (One Wait
State)
29.4.7 Burst Cycles
The device can be programmed to initiate burst cycles if its transfer size exceeds the port
size of the selected destination. The initiation of a burst cycle is encoded on the size pins.
For burst transfers to smaller port sizes, FB_TSIZ[1:0] indicates the size of the entire
transfer. For example, with bursting enabled, a 16-bit transfer to an 8-bit port takes two
beats (two byte-sized transfers), for which FB_TSIZ[1:0] equals 10b throughout. A 32-bit
transfer to an 8-bit port would take a 4-byte burst cycle, for which FB_TSIZ[1:0] equals
00b throughout.
With bursting disabled, any transfer larger than the port size breaks into multiple
individual transfers. With bursting enabled, an access larger than port size results in a
burst cycle of multiple beats. The following table shows the result of such transfer
translations.
Functional Description
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
714 Freescale Semiconductor, Inc.