Information

Address
Address Data
TSIZ
AA=1
AA=0
AA=1
AA=0
DataData Data
Add+1 Add+2 Add+3
FB_CLK
FB_A[Y]
FB_D[X]
FB_RW
FB_TS
FB_ALE
FB_CSn
FB_OEn
FB_BE/BWEn
FB_TA
FB_TSIZ[1:0]
Figure 29-46. 32-bit-Write Burst to 8-Bit Port 3-1-1-1 (No Wait States)
The following figure shows a 32-bit read from an 8-bit device with burst inhibited. The
transfer results in four individual transfers. The transfer size is driven at 32-bit (00)
during the first transfer and at byte (01) during the next three transfers.
Note
There is an extra clock of address setup (AS) for each burst-
inhibited transfer between states S0 and S1.
Chapter 29 External Bus Interface (FlexBus)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 717