Information

Address
Address Data
TSIZ = 00
AA=1
AA=0
AA=1
AA=0
Data Data
Add+1 Add+2 Add+3
Data
FB_CLK
FB_A[Y]
FB_D[X]
FB_RW
FB_TS
FB_ALE
FB_CSn
FB_OEn
FB_BE/BWEn
FB_TA
FB_TSIZ[1:0]
Figure 29-50. 32-bit-Write Burst to 8-Bit Port 3-2-2-2 (One Wait State)
If address setup and hold are used, only the first and last beat of the burst cycle are
affected. The following figure shows a read cycle with one clock of address setup and
address hold.
Note
In non-multiplexed address/data mode, the address on FB_A
increments only during internally-terminated burst cycles
(CSCRn[AA] = 1). The attached device must be able to account
for this, or a wait state must be added. The first address is
driven throughout the entire burst for externally-terminated
cycles.
In multiplexed address/data mode, the address is driven on
FB_AD only during the first cycle for internally- and
externally-terminated cycles.
Chapter 29 External Bus Interface (FlexBus)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 721