Information

ADCx_SC1n field descriptions (continued)
Field Description
6
AIEN
Interrupt enable
AIEN enables conversion complete interrupts. When COCO becomes set while the respective AIEN is
high, an interrupt is asserted.
0 Conversion complete interrupt disabled.
1 Conversion complete interrupt enabled.
5
DIFF
Differential mode enable
DIFF configures the ADC to operate in differential mode. When enabled, this mode automatically selects
from the differential channels, and changes the conversion algorithm and the number of cycles to
complete a conversion.
0 Single-ended conversions and input channels are selected.
1 Differential conversions and input channels are selected.
4–0
ADCH
Input channel select
The ADCH bits form a 5-bit field that selects one of the input channels. The input channel decode
depends on the value of the DIFF bit. DAD0-DAD3 are associated with the input pin pairs DADPx and
DADMx.
The successive approximation converter subsystem is turned off when the channel select bits are all set
(ADCH = 11111). This feature allows for explicit disabling of the ADC and isolation of the input channel
from all sources. Terminating continuous conversions this way prevents an additional single conversion
from being performed. It is not necessary to set the channel select bits to all ones to place the ADC in a
low-power state when continuous conversions are not enabled because the module automatically enters
a low-power state when a conversion completes.
00000 When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input.
00001 When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input.
00010 When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input.
00011 When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input.
00100 When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved.
00101 When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved.
00110 When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved.
00111 When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved.
01000 When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved.
01001 When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved.
01010 When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved.
01011 When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved.
01100 When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved.
01101 When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved.
01110 When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved.
01111 When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved.
10000 When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved.
10001 When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved.
10010 When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved.
10011 When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved.
10100 When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved.
10101 When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved.
10110 When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved.
Table continues on the next page...
Register Definition
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
756 Freescale Semiconductor, Inc.