Information

32.3.3 Configuration register 2 (ADCx_CFG2)
CFG2 register selects the special high speed configuration for very high speed
conversions and selects the long sample time duration during long sample mode.
Addresses: ADC0_CFG2 is 4003_B000h base + Ch offset = 4003_B00Ch
ADC1_CFG2 is 400B_B000h base + Ch offset = 400B_B00Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0 0
MUXSEL
ADACKEN
ADHSC
ADLSTS
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ADCx_CFG2 field descriptions
Field Description
31–8
Reserved
This read-only field is reserved and always has the value zero.
7–5
Reserved
This read-only field is reserved and always has the value zero.
4
MUXSEL
ADC Mux select
ADC Mux select bit is used to change the ADC mux setting to select between alternate sets of ADC
channels.
0 ADxxa channels are selected.
1 ADxxb channels are selected.
3
ADACKEN
Asynchronous clock output enable
ADACKEN enables the ADC's asynchronous clock source and the clock source output regardless of the
conversion and input clock select (ADICLK bits) status of the ADC. Based on MCU configuration, the
asynchronous clock may be used by other modules (see Chip Configuration information). Setting this bit
allows the clock to be used even while the ADC is idle or operating from a different clock source. Also,
latency of initiating a single or first-continuous conversion with the asynchronous clock selected is
reduced since the ADACK clock is already operational.
0 Asynchronous clock output disabled; Asynchronous clock only enabled if selected by ADICLK and a
conversion is active.
1 Asynchronous clock and clock output enabled regardless of the state of the ADC.
2
ADHSC
High speed configuration
Table continues on the next page...
Chapter 32 Analog-to-Digital Converter (ADC)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 759