Information

32.3.18 ADC PGA register (ADCx_PGA)
Addresses: ADC0_PGA is 4003_B000h base + 50h offset = 4003_B050h
ADC1_PGA is 400B_B000h base + 50h offset = 400B_B050h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
PGAEN
0
PGALPb
PGAG
W
0
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ADCx_PGA field descriptions
Field Description
31–24
Reserved
This read-only field is reserved and always has the value zero.
23
PGAEN
PGA enable
0 PGA disabled.
1 PGA enabled.
22
Reserved
This read-only field is reserved and always has the value zero.
21
Reserved
This field is reserved.
20
PGALPb
PGA low-power mode control
0 PGA runs in low power mode.
1 PGA runs in normal power mode.
19–16
PGAG
PGA gain setting
PGA gain = 2^(PGAG)
0000 1
0001 2
0010 4
0011 8
0100 16
0101 32
0110 64
0111 Reserved
Table continues on the next page...
Chapter 32 Analog-to-Digital Converter (ADC)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 771