Information

up the MCU from any non-VLLSx mode with the NMI function selected in its port control register asserts an NMI exception
on low power mode recovery. The same occurs when recovering from VLLSx modes if EzPort is disabled; otherwise,
EzPort mode is entered. See the "EzPort Configuration" section in this chapter for more information.
2. Requires the peripheral and the peripheral interrupt to be enabled. The LLWU's WUME bit enables the internal module flag
as a wakeup input. After wakeup, the flags are cleared based on the peripheral clearing mechanism.
3.3.5 MCM Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Miscellaneous
Control Module
(MCM)
Transfers
ARM Cortex-M4
core
PPB
Figure 3-9. MCM configuration
Table 3-14. Reference links to related information
Topic Related module Reference
Full description Miscellaneous control
module (MCM)
MCM
System memory map System memory map
Clocking Clock distribution
Power management Power management
Transfers
Private Peripheral Bus
(PPB)
ARM Cortex-M4 core ARM Cortex-M4 core
3.3.6 Crossbar Switch Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
System modules
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
78 Freescale Semiconductor, Inc.