Information

32.4.5.6 Conversion time examples
The following examples use Figure 32-95 and the information provided in Table 32-107
through Table 32-111.
32.4.5.6.1 Typical conversion time configuration
A typical configuration for ADC conversion is: 10-bit mode, with the bus clock selected
as the input clock source, the input clock divide-by-1 ratio selected, and a bus frequency
of 8 MHz, long sample time disabled and high speed conversion disabled. The
conversion time for a single conversion is calculated by using Figure 32-95 and the
information provided in Table 32-107 through Table 32-111. The table below list the
variables of Figure 32-95.
Table 32-112. Typical conversion time
Variable Time
SFCAdder 5 ADCK cycles + 5 bus clock cycles
AverageNum 1
BCT 20 ADCK cycles
LSTAdder 0
HSCAdder 0
The resulting conversion time is generated using the parameters listed in the proceeding
table. Therefore, for a bus clock equal to 8 MHz and an ADCK equal to 8 MHz the
resulting conversion time is 3.75 µs.
32.4.5.6.2 Long conversion time configuration
A configuration for long ADC conversion is: 16-bit differential mode with the bus clock
selected as the input clock source, the input clock divide-by-8 ratio selected, a bus
frequency of 8 MHz, long sample time enabled, configured for longest adder, high speed
conversion disabled, and average enabled for 32 conversions. The conversion time for
this conversion is calculated by using Figure 32-95 and the information provided in Table
32-107 through Table 32-111. The following table lists the variables of the Figure 32-95.
Table 32-113. Typical conversion time
Variable Time
SFCAdder 3 ADCK cycles + 5 bus clock cycles
AverageNum 32
BCT 34 ADCK cycles
LSTAdder 20 ADCK cycles
Table continues on the next page...
Functional description
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
784 Freescale Semiconductor, Inc.