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frequency characteristics. This capacitor is connected between V
REFH
and V
REFL
and
must be placed as near as possible to the package pins. Resistance in the path is not
recommended because the current causes a voltage drop that could result in conversion
errors. Inductance in this path must be minimum (parasitic only).
32.6.1.3 Analog input pins
The external analog inputs are typically shared with digital I/O pins on MCU devices.
Empirical data shows that capacitors on the analog inputs improve performance in the
presence of noise or when the source impedance is high. Use of 0.01 μF capacitors with
good high-frequency characteristics is sufficient. These capacitors are not necessary in all
cases, but when used they must be placed as near as possible to the package pins and be
referenced to V
SSA
.
For proper conversion, the input voltage must fall between V
REFH
and V
REFL
. If the input
is equal to or exceeds V
REFH
, the converter circuit converts the signal to 0xFFF (full scale
12-bit representation), 0x3FF (full scale 10-bit representation) or 0xFF (full scale 8-bit
representation). If the input is equal to or less than V
REFL
, the converter circuit converts it
to 0x000. Input voltages between V
REFH
and V
REFL
are straight-line linear conversions.
There is a brief current associated with V
REFL
when the sampling capacitor is charging.
For minimal loss of accuracy due to current injection, pins adjacent to the analog input
pins should not be transitioning during conversions.
32.6.2 Sources of error
Several sources of error exist for A/D conversions. These are discussed in the following
sections.
32.6.2.1 Sampling error
For proper conversions, the input must be sampled long enough to achieve the proper
accuracy.
RAS + RADIN =SC / (FMAX * NUMTAU * CADIN)
Figure 32-98. Sampling equation
Where:
RAS = External analog source resistance
Chapter 32 Analog-to-Digital Converter (ADC)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 797