Information

Table 3-15. Reference links to related information (continued)
Topic Related module Reference
Crossbar switch slave FlexBus FlexBus
3.3.6.1 Crossbar Switch Master Assignments
The masters connected to the crossbar switch are assigned as follows:
Master module Master port number
ARM core code bus 0
ARM core system bus 1
DMA/EzPort 2
SDHC 5
NOTE
The DMA and EzPort share a master port. Since these modules
never operate at the same time, no configuration or arbitration
explanations are necessary.
3.3.6.2 Crossbar Switch Slave Assignments
The slaves connected to the crossbar switch are assigned as follows:
Slave module Slave port number Protected by MPU?
Flash memory controller 0 Yes
SRAM backdoor 1 Yes
Peripheral bridge 0
1
2 No. Protection built into bridge.
Peripheral bridge 1/GPIO
1
3 No. Protection built into bridge.
FlexBus 4 Yes
1. See System memory map for access restrictions.
3.3.6.3 PRS register reset values
The AXBS_PRSn registers reset to 0054_3210h.
3.3.7 Memory Protection Unit (MPU) Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
System modules
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
80 Freescale Semiconductor, Inc.