Information

• If enabled, the Filter Block will incur up to 1 bus clock additional latency penalty on
COUT due to the fact that COUT (which is crossing clock domain boundaries) must
be resynchronized to the bus clock.
• CR1[WE] and CR1[SE] are mutually exclusive.
33.7 Memory Map/Register Definitions
CMP memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4007_3000 CMP Control Register 0 (CMP0_CR0) 8 R/W 00h
33.7.1/
809
4007_3001 CMP Control Register 1 (CMP0_CR1) 8 R/W 00h
33.7.2/
810
4007_3002 CMP Filter Period Register (CMP0_FPR) 8 R/W 00h
33.7.3/
811
4007_3003 CMP Status and Control Register (CMP0_SCR) 8 R/W 00h
33.7.4/
812
4007_3004 DAC Control Register (CMP0_DACCR) 8 R/W 00h
33.7.5/
813
4007_3005 MUX Control Register (CMP0_MUXCR) 8 R/W 00h
33.7.6/
814
4007_3008 CMP Control Register 0 (CMP1_CR0) 8 R/W 00h
33.7.1/
809
4007_3009 CMP Control Register 1 (CMP1_CR1) 8 R/W 00h
33.7.2/
810
4007_300A CMP Filter Period Register (CMP1_FPR) 8 R/W 00h
33.7.3/
811
4007_300B CMP Status and Control Register (CMP1_SCR) 8 R/W 00h
33.7.4/
812
4007_300C DAC Control Register (CMP1_DACCR) 8 R/W 00h
33.7.5/
813
4007_300D MUX Control Register (CMP1_MUXCR) 8 R/W 00h
33.7.6/
814
4007_3010 CMP Control Register 0 (CMP2_CR0) 8 R/W 00h
33.7.1/
809
4007_3011 CMP Control Register 1 (CMP2_CR1) 8 R/W 00h
33.7.2/
810
Table continues on the next page...
Memory Map/Register Definitions
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
808 Freescale Semiconductor, Inc.