Information

CMP memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4007_3012 CMP Filter Period Register (CMP2_FPR) 8 R/W 00h
33.7.3/
811
4007_3013 CMP Status and Control Register (CMP2_SCR) 8 R/W 00h
33.7.4/
812
4007_3014 DAC Control Register (CMP2_DACCR) 8 R/W 00h
33.7.5/
813
4007_3015 MUX Control Register (CMP2_MUXCR) 8 R/W 00h
33.7.6/
814
33.7.1 CMP Control Register 0 (CMPx_CR0)
Addresses: CMP0_CR0 is 4007_3000h base + 0h offset = 4007_3000h
CMP1_CR0 is 4007_3008h base + 0h offset = 4007_3008h
CMP2_CR0 is 4007_3010h base + 0h offset = 4007_3010h
Bit 7 6 5 4 3 2 1 0
Read 0
FILTER_CNT
0 0
HYSTCTR
Write
Reset
0 0 0 0 0 0 0 0
CMPx_CR0 field descriptions
Field Description
7
Reserved
This read-only field is reserved and always has the value zero.
6–4
FILTER_CNT
Filter Sample Count
These bits represent the number of consecutive samples that must agree prior to the comparator ouput
filter accepting a new output state. For information regarding filter programming and latency reference the
Functional Description.
000 Filter is disabled. If SE = 1, then COUT is a logic zero (this is not a legal state, and is not
recommended). If SE = 0, COUT = COUTA.
001 1 consecutive sample must agree (comparator output is simply sampled).
010 2 consecutive samples must agree.
011 3 consecutive samples must agree.
100 4 consecutive samples must agree.
101 5 consecutive samples must agree.
110 6 consecutive samples must agree.
111 7 consecutive samples must agree.
3
Reserved
This read-only field is reserved and always has the value zero.
Table continues on the next page...
Chapter 33 Comparator (CMP)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 809