Information

Memory Protection
Unit (MPU)
Transfers
Slave
Slave
Slave
Peripheral
bridge 0
Register
access
Transfers
Logical
Master
Logical
Master
Logical
Master
Figure 3-11. Memory Protection Unit configuration
Table 3-16. Reference links to related information
Topic Related module Reference
Full description Memory Protection Unit
(MPU)
MPU
System memory map System memory map
Clocking Clock distribution
Power management Power management
Logical masters Logical master assignments
Slave modules Slave module assignments
3.3.7.1 MPU Slave Port Assignments
The memory-mapped resources protected by the MPU are:
Table 3-17. MPU Slave Port Assignments
Source MPU Slave Port Assignment Destination
Crossbar slave port 0 MPU slave port 0 Flash Controller
Crossbar slave port 1 MPU slave port 1 SRAM backdoor
Code Bus MPU slave port 2 SRAM_L frontdoor
System Bus MPU slave port 3 SRAM_U frontdoor
Crossbar slave port 4 MPU slave port 4 FlexBus
Chapter 3 Chip Configuration
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 81