Information

CMPx_CR0 field descriptions (continued)
Field Description
2
Reserved
This read-only field is reserved and always has the value zero.
1–0
HYSTCTR
Comparator hard block hysteresis control
Defines the programmable hysteresis level. The hysteresis values associated with each level is device-
specific. See the device's data sheet for the exact values.
00 Level 0
01 Level 1
10 Level 2
11 Level 3
33.7.2 CMP Control Register 1 (CMPx_CR1)
Addresses: CMP0_CR1 is 4007_3000h base + 1h offset = 4007_3001h
CMP1_CR1 is 4007_3008h base + 1h offset = 4007_3009h
CMP2_CR1 is 4007_3010h base + 1h offset = 4007_3011h
Bit 7 6 5 4 3 2 1 0
Read
SE WE
0
PMODE INV COS OPE EN
Write
Reset
0 0 0 0 0 0 0 0
CMPx_CR1 field descriptions
Field Description
7
SE
Sample Enable
At any given time, either SE or WE can be set. If a write to this register attempts to set both, then SE is
set and WE is cleared. However, avoid writing ones to both bit locations because this "11" case is
reserved and may change in future implementations.
0 Sampling mode not selected.
1 Sampling mode selected.
6
WE
Windowing Enable
At any given time, either SE or WE can be set. If a write to this register attempts to set both, then SE is
set and WE is cleared. However, avoid writing ones to both bit locations because this "11" case is
reserved and may change in future implementations.
0 Windowing mode not selected.
1 Windowing mode selected.
5
Reserved
This read-only field is reserved and always has the value zero.
4
PMODE
Power Mode Select
Table continues on the next page...
Memory Map/Register Definitions
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
810 Freescale Semiconductor, Inc.