Information

CMPx_DACCR field descriptions
Field Description
7
DACEN
DAC Enable
This bit is used to enable the DAC. When the DAC is disabled, it is powered down to conserve power.
0 DAC is disabled.
1 DAC is enabled.
6
VRSEL
Supply Voltage Reference Source Select
0 V
in1
is selected as resistor ladder network supply reference Vin.
1 V
in2
is selected as resistor ladder network supply reference Vin.
5–0
VOSEL
DAC Output Voltage Select
This bit selects an output voltage from one of 64 distinct levels.
DACO = (Vin/64) * (VOSEL[5:0] + 1), so the DACO range is from Vin/64 to Vin.
33.7.6 MUX Control Register (CMPx_MUXCR)
PEN and MEN bits should be enabled or disabled together with CR1[EN] bit.
Addresses: CMP0_MUXCR is 4007_3000h base + 5h offset = 4007_3005h
CMP1_MUXCR is 4007_3008h base + 5h offset = 4007_300Dh
CMP2_MUXCR is 4007_3010h base + 5h offset = 4007_3015h
Bit 7 6 5 4 3 2 1 0
Read
PEN MEN PSEL MSEL
Write
Reset
0 0 0 0 0 0 0 0
CMPx_MUXCR field descriptions
Field Description
7
PEN
PMUX Enable
This bit is used to enable positive MUX. When the PMUX is disabled, the PMUX output is in a high
impedance state. When software selects the same input for plus and minus inputs of the comparator, both
PMUX and MMUX are disabled automatically.
0 PMUX is disabled.
1 PMUX is enabled.
6
MEN
MMUX Enable
This bit is used to enable negative MUX. When the MMUX is disabled, the MMUX output is in a high
impedance state. When software selects the same input for plus and minus inputs of the comparator, both
PMUX and MMUX are disabled automatically.
0 MMUX is disabled.
1 MMUX is enabled.
Table continues on the next page...
Memory Map/Register Definitions
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
814 Freescale Semiconductor, Inc.