Information

Table 3-20. Reset Values for RGD0 Registers

RGD0_WORD0 0000_0000h

RGD0_WORD1 FFFF_FFFFh

RGD0_WORD2 0061_F7DFh

RGD0_WORD3 0000_0001h

RGDAAC0 0061_F7DFh

3.3.7.5 Write Access Restrictions for RGD0 Registers

In addition to configuring the initial state of RGD0, the MPU implements further access

control on writes to the RGD0 registers. Specifically, the MPU assigns a priority scheme

where the debugger is treated as the highest priority master followed by the core and then

all the remaining masters.

The MPU does not allow writes from the core to affect the RGD0 start or end addresses

nor the permissions associated with the debugger; it can only write the permission fields

associated with the other masters.

These protections (summarized below) guarantee that the debugger always has access to

the entire address space and those rights cannot be changed by the core or any other bus

master.

Table 3-21. Write Access to RGD0 Registers

Bus Master Write Access?

Core Partial. The Core cannot write to the following registers or

• RGD0_WORD0, RGD0_WORD1, RGD0_WORD3

• RGD0_WORD2[M1SM, M1UM]

• RGDAAC0[M1SM, M1UM]

NOTE: Changes to the RGD0_WORD2 alterable fields

should be done via a write to RGDAAC0.

Debugger Yes

All other masters No

3.3.8 Peripheral Bridge Configuration

This section summarizes how the module has been configured in the chip. For a

comprehensive description of the module itself, see the module’s dedicated chapter.

Chapter 3 Chip Configuration

K10 Sub-Family Reference Manual, Rev. 6, Nov 2011

Freescale Semiconductor, Inc. 83