Information

DAC memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
400C_D018 DAC Data Low Register (DAC1_DAT12L) 8 R/W 00h
34.4.1/
838
400C_D019 DAC Data High Register (DAC1_DAT12H) 8 R/W 00h
34.4.2/
839
400C_D01A DAC Data Low Register (DAC1_DAT13L) 8 R/W 00h
34.4.1/
838
400C_D01B DAC Data High Register (DAC1_DAT13H) 8 R/W 00h
34.4.2/
839
400C_D01C DAC Data Low Register (DAC1_DAT14L) 8 R/W 00h
34.4.1/
838
400C_D01D DAC Data High Register (DAC1_DAT14H) 8 R/W 00h
34.4.2/
839
400C_D01E DAC Data Low Register (DAC1_DAT15L) 8 R/W 00h
34.4.1/
838
400C_D01F DAC Data High Register (DAC1_DAT15H) 8 R/W 00h
34.4.2/
839
400C_D020 DAC Status Register (DAC1_SR) 8 R 02h
34.4.3/
839
400C_D021 DAC Control Register (DAC1_C0) 8 R/W 00h
34.4.4/
840
400C_D022 DAC Control Register 1 (DAC1_C1) 8 R/W 00h
34.4.5/
841
400C_D023 DAC Control Register 2 (DAC1_C2) 8 R/W 0Fh
34.4.6/
842
34.4.1 DAC Data Low Register (DACx_DATL)
Addresses: 400C_C000h base + 0h offset + (2d × n), where n = 0d to 15d
Bit 7 6 5 4 3 2 1 0
Read
DATA[7:0]
Write
Reset
0 0 0 0 0 0 0 0
DACx_DATnL field descriptions
Field Description
7–0
DATA[7:0]
When the DAC Buffer is not enabled, DATA[11:0] controls the output voltage based on the following
formula. Vout = Vin * (1 + DACDAT0[11:0])/4096
When the DAC Buffer is enabled, DATA is mapped to the 16-word buffer.
Memory Map/Register Definition
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
838 Freescale Semiconductor, Inc.