Information

34.4.2 DAC Data High Register (DACx_DATH)
Addresses: 400C_C000h base + 1h offset + (2d × n), where n = 0d to 15d
Bit 7 6 5 4 3 2 1 0
Read 0
DATA[11:8]
Write
Reset
0 0 0 0 0 0 0 0
DACx_DATnH field descriptions
Field Description
7–4
Reserved
This read-only field is reserved and always has the value zero.
3–0
DATA[11:8]
When the DAC Buffer is not enabled, DATA[11:0] controls the output voltage based on the following
formula. Vout = Vin * (1 + DACDAT0[11:0])/4096
When the DAC Buffer is enabled, DATA[11:0] is mapped to the 16-word buffer.
34.4.3 DAC Status Register (DACx_SR)
If DMA is enabled, the flags can be cleared automatically by DMA when the DMA
request is done. Write zero to a bit to clear it. Writing one has no effect. After reset
DACBFRPTF is set and can be cleared by software, if needed. The flags are set only
when the data buffer status is changed.
Addresses: DAC0_SR is 400C_C000h base + 20h offset = 400C_C020h
DAC1_SR is 400C_D000h base + 20h offset = 400C_D020h
Bit 7 6 5 4 3 2 1 0
Read 0
DACBFWMF DACBFRPTF DACBFRPBF
Write
Reset
0 0 0 0 0 0 1 0
DACx_SR field descriptions
Field Description
7–3
Reserved
This read-only field is reserved and always has the value zero.
Reserved
2
DACBFWMF
DAC buffer watermark flag
0 The DAC buffer read pointer has not reached the watermark level.
1 The DAC buffer read pointer has reached the watermark level.
1
DACBFRPTF
DAC buffer read pointer top position flag
Table continues on the next page...
Chapter 34 12-bit Digital-to-Analog Converter (DAC)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 839