Information

Peripherals
Transfers
AIPS-Lite
peripheral bridge
Transfers
Crossbar switch
Figure 3-12. Peripheral bridge configuration
Table 3-22. Reference links to related information
Topic Related module Reference
Full description Peripheral bridge
(AIPS-Lite)
Peripheral bridge (AIPS-Lite)
System memory map System memory map
Clocking Clock Distribution
Crossbar switch Crossbar switch Crossbar switch
3.3.8.1 Number of peripheral bridges
This device contains two identical peripheral bridges.
3.3.8.2 Memory maps
The peripheral bridges are used to access the registers of most of the modules on this
device. See AIPS0 Memory Map and AIPS1 Memory Map for the memory slot
assignment for each module.
3.3.8.3 MPRA register
Each of the two peripheral bridges supports up to 8 crossbar switch masters, each
assigned to a MPROTx field in the MPRA register. However, fewer are supported on this
device. See Crossbar switch for details of the master port assignments for this device.
3.3.8.4 AIPS_Lite MPRA register reset value
• AIPSx_MPRA reset value is 0x7770_0000
Therefore, masters 0, 1, and 2 are trusted bus masters after reset.
System modules
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
84 Freescale Semiconductor, Inc.