Information

DACx_SR field descriptions (continued)
Field Description
0 The DAC buffer read pointer is not zero.
1 The DAC buffer read pointer is zero.
0
DACBFRPBF
DAC buffer read pointer bottom position flag
0 The DAC buffer read pointer is not equal to the DACBFUP.
1 The DAC buffer read pointer is equal to the DACBFUP.
34.4.4 DAC Control Register (DACx_C0)
Addresses: DAC0_C0 is 400C_C000h base + 21h offset = 400C_C021h
DAC1_C0 is 400C_D000h base + 21h offset = 400C_D021h
Bit 7 6 5 4 3 2 1 0
Read
DACEN DACRFS
DACTRGSEL
0
LPEN
DACBWIEN
DACBTIEN DACBBIEN
Write
DACSWTRG
Reset
0 0 0 0 0 0 0 0
DACx_C0 field descriptions
Field Description
7
DACEN
DAC enable
The DACEN bit starts the Programmable Reference Generator operation.
0 The DAC system is disabled.
1 The DAC system is enabled.
6
DACRFS
DAC Reference Select
0 The DAC selets DACREF_1 as the reference voltage.
1 The DAC selets DACREF_2 as the reference voltage.
5
DACTRGSEL
DAC trigger select
0 The DAC hardware trigger is selected.
1 The DAC software trigger is selected.
4
DACSWTRG
DAC software trigger
Active high. This is a write-only bit, read it always be 0. If DAC software trigger is selected and buffer
enabled, write 1 to this bit will advance the buffer read pointer once.
0 The DAC soft trigger is not valid.
1 The DAC soft trigger is valid.
3
LPEN
DAC low power control
Refer to the device data sheet's 12-bit DAC electrical characteristics for details on the impact of the
modes below.
Table continues on the next page...
Memory Map/Register Definition
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
840 Freescale Semiconductor, Inc.