Information

DACx_C0 field descriptions (continued)
Field Description
0 high power mode.
1 low power mode.
2
DACBWIEN
DAC buffer watermark interrupt enable
0 The DAC buffer watermark interrupt is disabled.
1 The DAC buffer watermark interrupt is enabled.
1
DACBTIEN
DAC buffer read pointer top flag interrupt enable
0 The DAC buffer read pointer top flag interrupt is disabled.
1 The DAC buffer read pointer top flag interrupt is enabled.
0
DACBBIEN
DAC buffer read pointer bottom flag interrupt enable
0 The DAC buffer read pointer bottom flag interrupt is disabled.
1 The DAC buffer read pointer bottom flag interrupt is enabled.
34.4.5 DAC Control Register 1 (DACx_C1)
Addresses: DAC0_C1 is 400C_C000h base + 22h offset = 400C_C022h
DAC1_C1 is 400C_D000h base + 22h offset = 400C_D022h
Bit 7 6 5 4 3 2 1 0
Read
DMAEN
0
DACBFWM DACBFMD DACBFEN
Write
Reset
0 0 0 0 0 0 0 0
DACx_C1 field descriptions
Field Description
7
DMAEN
DMA enable select
0 DMA disabled.
1 DMA enabled. When DMA enabled, DMA request will be generated by original interrupts. And
interrupts will not be presented on this module at the same time.
6–5
Reserved
This read-only field is reserved and always has the value zero.
4–3
DACBFWM
DAC buffer watermark select
This bitfield controls when the DAC buffer watermark flag will be set. When the DAC buffer read pointer
reaches the word defined by this bitfield, from 1 to 4 words away from the upper limit (DACBUP), the DAC
buffer watermark flag will be set. This allows user configuration of the watermark interrupt.
00 1 word
01 2 words
10 3 words
11 4 words
Table continues on the next page...
Chapter 34 12-bit Digital-to-Analog Converter (DAC)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 841