Information

When the Voltage Reference is already enabled and stabilized, changing SC[MODE_LV]
will not clear SC[VREFST] but there will be some startup time before the output voltage
at the VREF_OUT pin has settled. This is the buffer start up delay (Tstup) and the value
is specified in the appropriate device data sheet. Also, there will be some settling time
when a step change of the load current is applied to the VREF_OUT pin.
When the 1.75V VREF regulator is disabled, the VREF_OUT voltage will be more
sensitive to supply voltage variation. It is recommended to use this regulator to achieve
optimum VREF_OUT performance.
Initialization/Application Information
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
854 Freescale Semiconductor, Inc.