Information

• Optional back-to-back mode operation, which enables the ADC conversions
complete to trigger the next PDB channel
• One programmable delay interrupt
• One sequence error interrupt
• One channel flag and one sequence error flag per pre-trigger
• DMA support
• Up to eight DAC interval triggers
• One interval trigger output per DAC
• One 16-bit delay interval register per DAC trigger output
• Optional bypass the delay interval trigger registers
• Optional external triggers
• Up to eight pulse outputs (pulse-out's)
• Pulse-out's can be enabled or disabled independently.
• Programmable pulse width
NOTE
The number of PDB input and output triggers are chip-specific.
Refer to the Chip Configuration information for details.
36.1.2 Implementation
In this chapter, the following letters refers to the number of output triggers.
• N — Total available number of PDB channels.
• n — PDB channel number, valid from 0 to N-1.
• M — Total available pre-trigger per PDB channel.
• m — Pre-trigger number, valid from 0 to M-1.
• X — Total number of DAC interval triggers.
• x — DAC interval trigger output number, valid from 0 to X-1.
Introduction
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
856 Freescale Semiconductor, Inc.