Information

• Y — Total number of Pulse-Out's.
• y — Pulse-Out number, valid value is 0 to Y-1.
NOTE
The number of module output triggers to core are chip-specific.
For module to core output triggers implementation, refer to the
Chip Configuration information.
36.1.3 Back-to-back Acknowledgement Connections
PDB back-to-back operation acknowledgment connections are chip-specific. For
implementation, refer to the Chip Configuration information.
36.1.4 DAC External Trigger Input Connections
The implementation of DAC external trigger inputs is chip-specific. Refer to the Chip
Configuration information for details.
36.1.5 Block Diagram
This diagram illustrates the major components of the PDB.
Chapter 36 Programmable Delay Block (PDB)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 857