Information

PDB Counter
Ch n pre-trigger 0
Ch n pre-trigger 1
CHnDLY1
CHnDLY0
SC[LDOK]
Figure 36-57. Registers Update with SC[LDMOD] = x1
36.4.6 Interrupts
PDB can generate two interrupts, PDB interrupt and PDB sequence error interrupt. The
following table summarizes the interrupts.
Table 36-57. PDB Interrupt Summary
Interrupt Flags Enable Bit
PDB Interrupt SC[PDBIF] SC[PDBIE] = 1 and
SC[DMAEN] = 0
PDB Sequence Error Interrupt CHnS[ERRm] SC[PDBEIE] = 1
36.4.7 DMA
If SC[DMAEN] is set, PDB can generate DMA transfer request when SC[PDBIF] is set.
When DMA is enabled, the PDB interrupt will not be issued.
36.5 Application Information
36.5.1 Impact of Using the Prescaler and Multiplication Factor on
Timing Resolution
Use of prescaler and multiplication factor greater than 1 limits the count/delay accuracy
in terms of peripheral clock cycles (to the modulus of the prescaler X multiplication
factor). If the multiplication factor is set to 1 and the prescaler is set to 2 then the only
Chapter 36 Programmable Delay Block (PDB)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 875