Information

37.3.2 Register Descriptions
This section consists of register descriptions in address order.
Accesses to reserved addresses result in transfer errors. Registers for absent channels are
considered reserved.
FTM memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4003_8000 Status and Control (FTM0_SC) 32 R/W 0000_0000h
37.3.3/
890
4003_8004 Counter (FTM0_CNT) 32 R/W 0000_0000h
37.3.4/
891
4003_8008 Modulo (FTM0_MOD) 32 R/W 0000_0000h
37.3.5/
892
4003_800C Channel (n) Status and Control (FTM0_C0SC) 32 R/W 0000_0000h
37.3.6/
893
4003_8010 Channel (n) Value (FTM0_C0V) 32 R/W 0000_0000h
37.3.7/
896
4003_8014 Channel (n) Status and Control (FTM0_C1SC) 32 R/W 0000_0000h
37.3.6/
893
4003_8018 Channel (n) Value (FTM0_C1V) 32 R/W 0000_0000h
37.3.7/
896
4003_801C Channel (n) Status and Control (FTM0_C2SC) 32 R/W 0000_0000h
37.3.6/
893
4003_8020 Channel (n) Value (FTM0_C2V) 32 R/W 0000_0000h
37.3.7/
896
4003_8024 Channel (n) Status and Control (FTM0_C3SC) 32 R/W 0000_0000h
37.3.6/
893
4003_8028 Channel (n) Value (FTM0_C3V) 32 R/W 0000_0000h
37.3.7/
896
4003_802C Channel (n) Status and Control (FTM0_C4SC) 32 R/W 0000_0000h
37.3.6/
893
4003_8030 Channel (n) Value (FTM0_C4V) 32 R/W 0000_0000h
37.3.7/
896
4003_8034 Channel (n) Status and Control (FTM0_C5SC) 32 R/W 0000_0000h
37.3.6/
893
4003_8038 Channel (n) Value (FTM0_C5V) 32 R/W 0000_0000h
37.3.7/
896
4003_803C Channel (n) Status and Control (FTM0_C6SC) 32 R/W 0000_0000h
37.3.6/
893
Table continues on the next page...
Memory Map and Register Definition
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
884 Freescale Semiconductor, Inc.