Information

Table 37-67. Mode, Edge, and Level Selection (continued)
DECAPEN COMBINE CPWMS MSnB:MSnA ELSnB:ELSnA Mode Configuration
0 0 0 0 1 Input capture Capture on
Rising Edge
Only
10 Capture on
Falling Edge
Only
11 Capture on
Rising or Falling
Edge
1 1 Output compare Toggle Output
on match
10 Clear Output on
match
11 Set Output on
match
1X 10 Edge-aligned
PWM
High-true
pulses (clear
Output on
match)
X1 Low-true pulses
(set Output on
match)
1 XX 10 Center-aligned
PWM
High-true
pulses (clear
Output on
match-up)
X1 Low-true pulses
(set Output on
match-up)
1 0 XX 10 Combine PWM High-true
pulses (set on
channel (n)
match, and
clear on
channel (n+1)
match)
X1 Low-true pulses
(clear on
channel (n)
match, and set
on channel (n
+1) match)
1 0 0 X0 See the
following table
(Table 37-8).
Dual Edge
Capture Mode
One-shot
capture mode
X1 Continuous
capture mode
Memory Map and Register Definition
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
894 Freescale Semiconductor, Inc.