Information

3.3.12.1 WDOG clocks
This table shows the WDOG module clocks and the corresponding chip clocks.
Table 3-30. WDOG clock connections
Module clock Chip clock
LPO Oscillator 1 kHz LPO Clock
Alt Clock Bus Clock
Fast Test Clock Bus Clock
System Bus Clock Bus Clock
3.3.12.2 WDOG low-power modes
This table shows the WDOG low-power modes and the corresponding chip low-power
modes.
Table 3-31. WDOG low-power modes
Module mode Chip mode
Wait Wait, VLPW
Standby Stop, VLPS
Stop Stop, VLPS
Power Down LLS, VLLSx
NOTE
To enable the WDOG module when the chip is in Stop mode,
write ones to both the STNDBYEN bit and the STOPEN bit of
the Watchdog Status and Control Register High.
Clock Modules
3.4.1 MCG Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
3.4
Chapter 3 Chip Configuration
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 91